Advanced FPGA Synthesis

Precision Synthesis offers high quality of results, industry-unique features, and integration across Mentor Graphics’ FPGA Flow– the industry’s most comprehensive FPGA vendor independent solution.



Precision RTL 
Precision RTL provides an intuitive logic synthesis environment and forms the centerpiece of the Mentor Graphics vendor-independent FPGA flow. With a rich feature set that includes advanced optimizations, award-winning analysis, and industry-leading language support, Precision RTL enables vendor-independent design, accelerates time to market, eliminates design defects, and delivers superior quality of results (QoR). 

Precision RTL Plus 
Precision RTL Plus offers an improved way of designing FPGAs and dramatically increasing designer productivity. This latest addition to the Precision family of products provides several industry-first capabilities that enable every designer, regardless of level of expertise, to reach timing closure faster, minimize the impact of design changes, and make efficient use of FPGA embedded blocks. 

Precision Physical 
Precision Physical features post-place-and-route physical synthesis to meet aggressive timing requirements for complex FPGA designs. Precision Physical also offers a powerful Placement Reuse/ECO feature allowing incremental changes while preserving timing constraints and producing predictable results. A super-set of all other product configurations, Precision Physical is the most advanced offering in the Precision Synthesis product suite. 

LeonardoSpectrum™ offers customers a well-proven, mature synthesis solution for both FPGAs and ASICs. 

ASIC Prototyping

With increasing competitive pressures and shorter product life cycles, designers have less time to develop high performance and complex ASIC designs.


At the same time, the development cost of an ASIC is increasing rapidly, making it less feasible to use ASIC devices for many cost-sensitive applications without extensive testing and simulation. As FPGA devices have become larger and faster, verifying functionality of costly ASIC designs in FPGAs has become an effective and economical method of verification. However, some ASIC structures cannot be directly implemented in an FPGA efficiently.


Precision Synthesis helps ease the transition from ASIC to FPGA design by allowing the same HDL code and constraint syntax to be used. To obtain optimal performance, automatic conversions of ASIC design structures are utilized.



Precision RTL Plus

Offers breakthrough advantages for both commercial applications and for mil-aero and safety-critical systems. Features include multi-vendor physical synthesis, incremental flows, low power synthesis, 

Design Creation

Whether designing an FPGA or ASIC, the devices have advanced capabilities and complex features that, when put under tight development cycles, burden the design teams to produce efficient and robust chips. Hence, the design teams have placed more demands on HDL processes, automation, and style guidelines for developing quality design results.

Standard languages (such as VHDL, Verilog, SystemVerilog) and IP formats, along with common industry version management systems aid in producing repeatable and dependable design processes, but the tools that utilize these standards need to do much more than edit text files. Mentor Graphics delivers a complete design solution for FPGA and ASIC HDL development beginning with comprehensive design creation addressing new code creation, formal and informal design reuse, and any combination in between. These HDL design capabilities greatly assist engineers, individuals and teams, in creating, analyzing, and managing their complex designs, improving their productivity and accelerating design creation.


HDL Designer
With deep analysis capabilities, advanced creation editors, and complete project and flow management, HDL Designer delivers a powerful HDL design environment.

Visual Elite HDL 
Built upon a strong HDL implementation infrastructure, Visual Elite HDL offers the most advanced electronic system-level (ESL) and transaction level modeling (TLM) concepts and mechanisms.


HDL Author 
HDL Author's advanced editors and HDL code visualization in graphical and tabular representations of the design, speed the design creation and analysis of FPGA and ASIC designs.


  • Optimizes Results with Advanced Creation & Analysis Technology
  • Reduces Design Cycles with Managed Data and Flow Integration
  • Maximizes Design Effort through Common Front End for FPGA and ASIC

Design Reuse

Effective design reuse is a critical objective for every electronic design company as 75% of future productivity gains will come through reuse. Executives, managers, and engineers all have a big stake in reuse, but nearly everyone underestimates the challenges associated with it.


Mentor Graphics offers products in the HDL Designer Series family that will, in minutes, automatically comprehend the design hierarchy, highlight syntax errors, point out missing or orphaned blocks, determine the quality of the HDL code, visualize the design to accelerate understanding of the design being reused, and prepare the new design for efficient future reuse, optionally in IP-XACT format.



HDL Designer

With deep analysis capabilities, advanced creation editors, and complete project and flow management, HDL Designer delivers a powerful HDL design environment. Learn More ►



  • Saves time by analyzing and correcting design integrity
  • Ensures the best reuse decision by measuring code quality
  • Accelerates design understanding of structure and behavior
  • Automates assembly of IP-XACT models
  • Generates IP-XACT enabled IP models
  • Extracts, packages and manages IP for future reuse

DO-254 Solutions

Mentor Graphics solutions deliver a best-practice methodology for requirements-based design, to help you meet your DO-254 quality objectives while improving the productivity of your flows and valuable resources.


  • Continuous requirements tracking throughout design and verification 
  • Efficient and compliant electronic hardware development and verification
  • Repeatable design development flow for consistent quality process
  • Extensive management and reporting for project management
  • Comprehensive documentation for projects and certification support
  • First project support, training, and consulting



RTCA/DO-254 "Design Assurance Guidance for Airborne Electronic Hardware" is a recent standard that is currently being enforced by the Federal Aviation Administration (FAA), European Aviation Safety Agency (EASA), and other worldwide aviation certification agencies. The purpose of DO-254 is to ensure the safety of in-flight hardware. All FPGA (or ASIC) devices that go in systems that fly must now adhere to the DO-254 standard. The stringency of the process is dictated by the design assurance level (DAL, or safety rating) of the end system, levels A (highest) through E (lowest).


Requirements Tracing

Requirements are handed down to the component from the system level in DO-254 flows. The ability to trace and manage design requirements from specification through implementation is beneficial to all projects and mandatory for DO-254 compliance. Mentor Graphics provides solutions for requirements tracing throughout the design process.



A key part of any design flow, Mentor offers a design creation solution that is highly tuned to the needs of DO-254 projects. With its features for RTL editing, code checking, and reuse assurance, its ability to produce design artifacts and web-based review/audit sites, along with its links to configuration management tools and other design tools in the flow, HDL Designer can provide a productive framework for DO-254 and other requirements-based design projects.



Synthesis is a transformation of the design, and ensuring this process is done as safely as possible is a high priority for safety-critical and DO-254 flows. For FPGA designers, Precision Synthesis® offers vendor-independent synthesis. Precision ensures reliable design operation with safe FSM encoding and radiation-hardened device support, while providing advanced optimization and award-winning analysis to meet aggressive performance and area goals.


Verifying that the device performs its intended function (and does not do anything unintended) is a crucial part of DO-254 flows. From the traditional favorite simulator ModelSim®, to the advanced verification platform of Questa®, Mentor's industry-leading advanced verification solution supports even the most complex designs, with requirements-based verification management and unified coverage database to meet both your DO-254 compliance and business goals.



Mentor Consulting has extensive experience helping companies achieve DO-254 compliance with hands-on services to accelerate success and reduce risk, especially in the areas of new verification methods and testbench creation. Our consultants are experts in SystemVerilog-based verification using Mentor's OVM/AVM methodology and advanced verification tool suite. Mentor Consulting works directly with your design and verification teams to assess their verification requirements, architect a verification environment specifically-suited to meeting those requirements, and help you implement a verification solution along with the planning and management necessary for first-pass success.

SystemVerilog Design & Synthesis

SystemVerilog is a powerful language that enables tremendous improvements in both advanced design and verification methodologies. However, to fully leverage the language, design and verification engineers need to become familiar with:


  • Object Oriented Programming Techniques
  • Methods for integrating existing VHDL and Verilog code
  • New constructs that enable coding at higher levels of abstraction


Adopting SystemVerilog as a language can prove to be a daunting task for many hardware designers unfamiliar with object-oriented language constructs. Mentor Graphics provides solutions that enable designers to leverage the power of SystemVerilog for productive design creation, effective testbench development, and efficient synthesis. These tools facilitate the understanding, creation and reuse of SystemVerilog code, providing a major productivity boost for both design and verification engineers working with SystemVerilog, AVM, and OVM-based environments.



Precision RTL Plus

Offers breakthrough advantages for both commercial applications and for mil-aero and safety-critical systems. Features include multi-vendor physical synthesis, incremental flows, low power synthesis


HDL Designer

With deep analysis capabilities, advanced creation editors, and complete project and flow management, HDL Designer delivers a powerful HDL design environment. 

Products A to Z - FPGA Design

DL Author 
Aids HDL entry via many graphical, tabular and textual editors, and generates code. 

HDL Designer 
Design creation/RTL Reuse and management environment for FPGA and ASIC design. 


LeonardoSpectrum™ offers customers a well-proven, mature synthesis solution for both FPGAs and ASICs.  


ModelSim's easy to use, unified debug and simulation environment gives today's FPGA designers advanced capabilities in a productive work environment.  

Precision Physical 
All of the capabilities of Precision RTL with advanced physical synthesis environment offering interactive placement optimization capabilities for complex FPGA designs that enhances FPGA designer productivity and allows rapid timing convergence. Precision Physical offers a powerful Placement Reuse/ECO feature allowing incremental changes that preserve timing constraints and maintain predictable results. 

Precision RTL 
An intuitive logic synthesis environment - Precision RTL.  

Precision RTL Plus 
Reach design goals faster and in fewer iterations - Precision RTL Plus. 

Manage requirements in your FPGA and ASIC design flows. ReqTracer simplifies, automates and enables requirements traceability from specification of the hardware specification through HDL coding, implementation and validation. 

Visual Elite HDL 
Continuous Design Flow from TLM to RTL - Visual Elite HDL. 

Requirements Tracing

Clearly tracking hardware implementation for specified requirement validation has become a preferred development practice that is well suited for safety critical projects in medical, transportation, aerospace and military, but is equally significant for any complex ASIC or FPGA design.



  • Control and predict project schedules
  • Trace requirements through HW design process
  • Clearly communicate via visualization and intuitive reports
  • Manage impact of requirement changes
  • Meet safety critical and DO-254 certification




Simplifies, automates and enables requirements traceability from specification of the hardware specification through HDL coding, implementation and validation.

Simulation & Verification

Advanced simulation and verification for today’s complex FPGA designs

FPGA devices have gone through radical changes in the last decade, becoming so complex they now resemble complete systems. As a result, they require advanced verification technology to improve FPGA debugging, deliver code coverage, and enhance verification throughput.

This change in FPGA capabilities has resulted in the emergence of advanced FPGA solutions, which include the integration of third-party IP, DSPs, and multiple processors, all connected through advanced high-speed bus protocols.

Mentor Graphics delivers the FPGA verification tools and expertise you need to get high-quality products out the door faster.



The combination of industry-leading, native SKS performance with the best integrated debug and analysis environment make ModelSim the simulator of choice for both ASIC and FPGA design.


ModelSim® Starter

Cost-effective, entry-level simulation for FPGA engineers, ModelSim Starter puts you on the right path for unified debug and simulation in FPGA design


Questa® Advanced Simulator

Combines high performance and capacity simulation with unified advanced debug capabilities for the most complete native support of Verilog, SystemVerilog, VHDL, SystemC, PSL and UPF.


Mentor® Verification IP

Comprehensive verification IP built using advanced methodologies for fastest time to verification sign-off.