Methodologies for Functional Verification

erification Methodologies form the backbone of a solid verification strategy. Mentor Graphics is actively driving advanced methodologies and their standardization across the industry.


Assertion Based Verification 
Assertion-based verification (ABV) is a methodology in which designers use assertions to capture specific design intent and, either through simulation, formal verification, or emulation of these assertions, verify that the design correctly implements that intent.

Open Verification Methodology 
The OVM is the first truly open, interoperable, and proven verification methodology based on the SystemVerilog IEEE 1800 language and delivers an open and unified class library and methodology for interoperable verification IP (VIP)

Processor-Driven Verification 
Current techniques of applying test vectors from an HDL testbench only begin to mimic processor bus behavior. The introduction of processor-driven test benches into the existing verification methodology enables real-world verification and extensive reuse of testbench 

Emulation Systems

The Veloce SoC verification system reduces project schedule and cost risk throughsimulation acceleration and high performance in-circuit emulation. The Veloce product line supports the Open Verification Methodology (OVM) and Assertion-based Verification (ABV). 

Value is delivered by:

  • Accelerating transaction-based and signal-level block and full SoC regression test runs by 100s to 1000s of times,
  • Providing a comprehensive, simulation-like debug environment
  • Providing a hardware platform for software development and debug months before first silicon is available,
  • Enabling full system integration using real-world data and software for test benches before first silicon availability,
  • Accelerating post-silicon validation by accelerating regression tests before committing changes to silicon, and
  • Eliminating most silicon re-spins due to functional errors.


The Veloce simulation acceleration/emulation product line has five scalable hardware configurations that can be configured to verify designs from 8 million gates up

to 512 million gates within a single chassis.



Comprehensive Verification Environment 
Veloce Systems have complementary software and application solutions to provide a comprehensive verification environment.provides a mixed-level modeling, co-simulation interface for Veloce and the Questa simulator, and other commercial simulators. HDL Link also enables ultra-fast simulation acceleration by automatically encapsulating simulation test benches in a C/C++ environment for regression testing using Veloce.

iSolve Application Solutions provide complementary solutions for memory modeling, embedded processors, software debug, multi-media data streaming and analysis and industry standard bus and communications interfaces.

Veloce Product Family

High-performance, high-capacity hardware-assisted solution for verifying embedded systems and SoC designs


TestBench XPress (TBX) is the Veloce co-modeling software application that makes the Veloce SoC verification system a transaction-level modeling(TLM) verification engine running up to 10,000x the speed of TLM software simulators.


HDL Link Software is an application that enables the Veloce system (1) to run in a mixed-level modeling, co-simulation mode with the Questa simulator and (2) to accelerate block-level and full SoC regression test runs by 100s of times in a free running acceleration mode (fast regression database mode-FRDB).


The iSolve family of application solutions consists of flexible, pre-configured software models and specialized hardware sub-systems for the Veloce product family. These models and sub-systems address the SoC modeling and real world testing requirements that are required for you to quickly build complete, high performance SoC verification environments.

Products A to Z - Functional Verification

Clock-Domain Crossing (CDC) Verification 
Designers increasingly use advanced multi-clocking architectures to meet the high-performance and low-power requirements of their chips. The 0-In® CDC verification solution focuses on the interaction between these clock domains.


Questa Formal Verification

The 0-In® Formal verification solution offers the highest capacity and performance available to help you find your most complex bugs.


FormalPro is the Mentor Graphics high-capacity equivalence checking solution for regression testing of ASICs and ICs. FormalPro uses formal verification techniques to prove that a design is equivalent to its golden reference model. 

HDL Designer 
HDL Designer provides engineers with a suite of advanced design editors to facilitate development: interface-based design spreadsheet editor (IBD) and block diagram, state-machine, truth table, flow chart and algorithmic state-machine editors.

Questa® inFact
inFact testbench synthesis provides a straightforward way to achieve higher coverage, while significantly reducing input code required to write a testbench.

ModelSim's easy to use, unified debug and simulation environment gives today's FPGA designers advanced capabilities in a productive work environment. 

Questa® Advanced Simulator
Questa is Mentor Graphic's Advanced Verification Environment and is the only integrated verification platform that can improve quality, productivity, and predictability for any verification flow. 

Questa ADMS
Questa ADMS is a language-neutral, mixed-signal simulator that enables top-down design and bottom-up verification of multi-million gate analog/mixed-signal system-on-chip designs. 

Questa Codelink is a graphical source-level debugger for code executing on RTL processor models from ARM and MIPS.


Mentor® Verification IP
With the pre-verified, configurable, and reusable verification components in the Questa MVC library, you can reduce the overall testbench development effort and free up time for testing your proprietary modules and functions. 

Seamless enables users to debug hardware/software integration issues early in the design cycle by running embedded software on a simulation model of the embedded hardware.

High-performance, high-capacity hardware-assisted solution for verifying embedded systems and SoC designs. 

Vista™ Architect, a superset of the Vista Design solution, is a complete TLM 2.0-based solution for architecture design and exploration enable system architects and SoC designers to make viable architecture decisions, prototype and analyze complex systems.

Visual Elite 
Visual Elite™ is the state-of-the-art design and integration platform enabling designers and system architects to intuitively capture and connect SystemC, TLM 2.0 and HDL blocks into complex SoC’s and systems.