Clock-Domain Crossing (CDC) Verification
Designers increasingly use advanced multi-clocking architectures to meet the high-performance and low-power requirements of their chips. The 0-In® CDC verification solution focuses on the interaction between these clock domains.
Questa Formal Verification
The 0-In® Formal verification solution offers the highest capacity and performance available to help you find your most complex bugs.
FormalPro is the Mentor Graphics high-capacity equivalence checking solution for regression testing of ASICs and ICs. FormalPro uses formal verification techniques to prove that a design is equivalent to its golden reference model.
HDL Designer provides engineers with a suite of advanced design editors to facilitate development: interface-based design spreadsheet editor (IBD) and block diagram, state-machine, truth table, flow chart and algorithmic state-machine editors.
inFact testbench synthesis provides a straightforward way to achieve higher coverage, while significantly reducing input code required to write a testbench.
ModelSim's easy to use, unified debug and simulation environment gives today's FPGA designers advanced capabilities in a productive work environment.
Questa® Advanced Simulator
Questa is Mentor Graphic's Advanced Verification Environment and is the only integrated verification platform that can improve quality, productivity, and predictability for any verification flow.
Questa ADMS is a language-neutral, mixed-signal simulator that enables top-down design and bottom-up verification of multi-million gate analog/mixed-signal system-on-chip designs.
Questa Codelink is a graphical source-level debugger for code executing on RTL processor models from ARM and MIPS.
Mentor® Verification IP
With the pre-verified, configurable, and reusable verification components in the Questa MVC library, you can reduce the overall testbench development effort and free up time for testing your proprietary modules and functions.
Seamless enables users to debug hardware/software integration issues early in the design cycle by running embedded software on a simulation model of the embedded hardware.
High-performance, high-capacity hardware-assisted solution for verifying embedded systems and SoC designs.
Vista™ Architect, a superset of the Vista Design solution, is a complete TLM 2.0-based solution for architecture design and exploration enable system architects and SoC designers to make viable architecture decisions, prototype and analyze complex systems.
Visual Elite™ is the state-of-the-art design and integration platform enabling designers and system architects to intuitively capture and connect SystemC, TLM 2.0 and HDL blocks into complex SoC’s and systems.