Digital IC Design

Innovative Technologies for Fast & High-Quality Design Closure at Advanced Process Nodes

 

Mentor Graphics IC implementation solutions, Olympus-SoC™ and Calibre® InRoute, deliver innovative technologies to solve the power, performance, capacity, time-to-market, and variability challenges encountered at the leading-edge process nodes.

 

The Olympus-SoC netlist-to-GDSII system performs variation- and power-aware rapid feasibility, including placement, advanced clock tree synthesis, and optimization for all mode/corner scenarios concurrently.

 

The Calibre InRoute design and verification platform includes all Olympus-SoC capabilities, plus true Calibre DRC and DFM signoff within the place and route environment.  
Benefits of Olympus tools:

  • Boost IC performance with advanced multi-corner, multi-mode (MCMM) optimization

  • Reduce power consumption in clock trees with MCMM clock tree synthesis

  • Improve yield with DFM-aware routing to address lithography issues in a timing context during implementation

  • Speed time-to-market with fewer design iterations, scalable multi-threading, and sign-off quality closure

  • Load and process designs of 100M gates or more with the industry's highest-capacity data structure

  • Reduce costs through high yields and fast time-to-market   Boost IC performance with advanced multi-corner, multi-mode (MCMM) optimization


Digital IC Design Products

Olympus-SoC

Olympus-SoC is a complete IC design-for-variability implementation solution targeted at 65nm/45nm designs. 

  

Calibre InRoute

Calibre InRoute enables designers to achieve signoff-quality manufacturing closure during physical design within the Olympus-SoC place and route system. 

 

Custom Design

Explore the Possibilities

Mentor’s new Pyxis Custom IC Design Platform includes integrated solutions for design capturefloorplanningcustom routingpolygon editingphysical layoutschematic-driven layoutconcurrent editing and chip assembly. To help companies jump-start their design cycles and cut time-to-market, Mentor Graphics and its foundry partners have developed design kits.

 

These kits include all the foundry-specific devices and models for use with Pyxis Custom IC Design solutions. The platform supports all common commercial design kit formats plus numerous customer proprietary formats. Mentor supports OpenPDK, iPDK and other industry standards.

 

The solutions in this platform are easily configured and offer an affordable option for design engineers.

 

 

Pyxis Concurrent enables multiple users to edit the same cell at the same time. Instead of placing the chip finishing duties solely in the hands of a single layout engineer, Pyxis Concurrent allows the... View Video ►

 

 

Pyxis Custom Router, an add-on option for Pyxis Implement, introduces an integrated tool box of advanced custom routing functionality. The tool box includes a global router for congestion mitigation, a... View Video ►

 


 


Custom IC Design Products

Pyxis Schematic

Pyxis Schematic, part of Mentor's new Pyxis Custom IC Design Platform, provides a powerful and easy-to-use design entry environment with advanced capabilities that boost designer productivity.

 

Pyxis Implement

Pyxis Implement, part of Mentor's new Pyxis Custom IC Design Platform, provides a highly productive environment for correct by construction layout entry and editing.

 

Pyxis Layout

Pyxis Layout, part of Mentor's new Pyxis Custom IC Design Platform, provides a fast and flexible environment for layout entry and editing. 

Analog/Mixed-Signal Verification

Mentor's analog/mixed-signal verification tools offer a language-neutral verification environment for complex analog/mixed-signal System-on-Chip designs. Questa ADMS combines four high performance simulation engines in one efficient tool: Eldo Classic for general purpose analog simulations, Questa for digital simulations, ADiT™ for fast transistor-level simulations and Eldo RF for radio frequency simulations. Additionally, Mentor's recently released Faster-SPICE solution, Eldo Premier, providing increased performance and capacity, especially for very large circuits, without sacrificing accuracy. These technologies enable top-down design and bottom-up verification of multi-million gate AMS SoC designs.


AMS Design & Verification

Questa ADMS
Language-neutral, mixed-signal simulator that enables top-down design and bottom-up verification of multi-million gate analog/mixed-signal System-on-Chip designs. 

 

Questa ADMS RF

Integrated RF and Mixed Signal Simulation for Complete Verification of RF-DSP Systems. 

 

Eldo Classic
When accuracy matters designers choose Eldo Classic, Mentor’s “golden” SPICE accurate circuit simulator, designed to address the complex needs of analog and mixed-signal designers. 

 

Eldo Premier

Mentor’s new Faster-SPICE product, addresses the primary concerns of analog and mixed-signal designers, providing increased performance and capacity, especially for very large circuits, without sacrificing accuracy. 

 

Eldo RF

Eldo RF : Transistor-level simulator for RF IC designs. 

 

ADiT
ADiT is a fast-SPICE simulation tool that delivers the ability to obtain accurate and reliable simulation results 10X – 100X faster than traditional SPICE tools. 

 

Analog FastSPICE  (AFS)
The world’s fastest nanometer circuit verification platform for analog, RF, mixed-signal, and custom digital circuits.

 

Related Products

ICanalyst
A "checkerboard" verification (CV) methodology, supported by the Questa ADMS platform, is a technique of configuring SPICE and abstract behavioral models where possible to validate efficiently a full-chip mixed-signal circuit, yet retain near-SPICE accuracy. 


EZwave 
An advanced graphical user interface that displays and analyzes analog, digital, and mixed-signal waveform databases.


Artist Link 
An integration tool links MGC SPICE/Mixed-Signal Simulation tools to Cadence Analog Artist environment.


Time-it
Independent delay calculation tool that is used in a back-end design flow with the Mentor Graphics analog/mixed-signal tool suite. 

IC Verification & Signoff Using Calibre

Mentor's IC verification and sign-off includes not only traditional rule-based physical verification and parasitic extraction, but also new capabilities and automated technologies that help improve yield by enhancing the design itself.

Calibre® is the overwhelming market share leader and the industry standard for IC physical verification, due to the outstanding performance, accuracy and reliability of Calibre products. Over the last two years, Calibre nmDRC™ has reduced average DRC runtime by a factor of five, while Calibre's innovative Hyperscaling and MTFlex™ technologies have cut memory requirements in half. Calibre nmDRC also reduced overall cycle time with incremental DRC, which allows designers to make DRC runs in parallel. As DRC violations are reported, designers can immediately fix and recheck just the affected areas, while the initial DRC run continues.

To handle complex and multi-variate, multi-dimensional checks that are not adequately addressed by traditional design rules, Calibre nmDRC's equation-based DRC (eqDRC) capability enables designers to express design rule checks as continuous, multi-dimensional functions that accurately and precisely reflect underlying physical interactions. With eqDRC, designers can use Calibre nmDRC to address complex DFM issues that other DRC tools simply can't handle.

Calibre nmLVS provides actual device geometry measurement, programmable electrical rule checking, and sophisticated interactive debugging capabilities to ensure accurate circuit verification and further improve the designer's productivity.


Features and Benefits

  • The underlying hierarchical processing engine ensures robust testing and implementation across all applications, while providing best-in-class runtimes.
  • Common design platform integration enables rapid deployment of all Calibre nm Platform applications into the user’s design environment.
  • Integrated scripting environment across all applications (SVRF and TVF) allow users to customize their design and verification environment to suit the specific and evolving needs of their design teams.
  • Hyperscaling technology brings superior scalability and lightning fast-run times for computationally intense applications, while reducing capital expenditures by extending the useful life of existing shared memory processor systems, and fully utilizing inexpensive distributed rack systems.


Physical Verification Products

Calibre's physical verification capabilities are the industry standard for accuracy, reliability, and performance. Learn More ►

Calibre nmLVS
The industry-standard physical verification tool for layout vs. schematic comparison combines accurate circuit verification with fast runtimes and interactive debugging.

 

Calibre nmDRC 
The industry standard for design rule checking provides fast cycle times and innovative design rule capabilities

 

Calibre Interactive™
The Calibre Interactive™ invocation GUI provides users with fast and easy access to the Calibre® tool suite, enabling designers to perform physical verification and parasitic extraction from within their familiar IC design environment.

 

Calibre InRoute

Calibre InRoute enables designers to achieve signoff-quality manufacturing closure during physical design within the Olympus-SoC place and route system.

 

Calibre RVE™

Calibre RVE™ provides a graphical results viewing environment that can be used with all Calibre tools and popular design layout tools to reduce debug time by visually identifying design errors instantly in the user’s own design environment.

 

Calibre Pattern Matching

Calibre® Pattern Matching replaces text-based design rule checks with a visual geometry that ensures a precise and accurate implementation of the design specification.

 

Calibre DESIGNrev™
The Calibre DESIGNrev layout editor speeds full-chip design completions and tape-outs by rapidly loading, displaying and saving large GDSII and OASIS files.

 

Calibre InRoute

Calibre InRoute enables designers to achieve signoff-quality manufacturing closure during physical design within the Olympus-SoC place and route system.

 

Calibre Automatic Waivers

Calibre® Automatic Waiver provides automated recognition and removal of waived design rule violations during DRC. Calibre Automatic Waivers eliminates costly time and effort from the verification process, and ensures accurate processing of all waiver information on every DRC run. .

  

Calibre RealTime

Calibre® RealTime enables on-demand Calibre signoff design rule checking (DRC) for custom and analog/mixed-signal design flows, improving both design speed and the quality of results by providing immediate feedback on design rule violations and recommended rule compliance. 

 

Circuit Verification Products

Calibre's circuit verification strategies and tools effectively and efficiently address the reliability and functional yield challenges of today’s advanced and complex IC designs. Learn More ►

Calibre nmLVS 
The industry-standard physical verification tool for layout vs. schematic comparison combines accurate circuit verification with fast runtimes and interactive debugging.

 

Calibre xRC
Calibre xRC™ offers a robust parasitic extraction tool that delivers accurate parasitic data for comprehensive and accurate post-layout analysis and simulation.

 

Calibre xL
Full-chip, fast, and accurate extraction of frequency dependent loop inductance and loop resistance and automatically accounts for return path change with frequency. Fully integrated with Calibre nmLVS and xRC.

 

Calibre PERC
Industry’s only programmable electrical rule checking (PERC) tool designed to address advanced verification requirements to ensure optimal design yield and improve reliability.

Design for Manufacturing with Calibre

Calibre is Broadest, Most Accurate, and Best Performing DFM Solution in the Industry.
At nanometer nodes, design signoff is no longer just DRC and LVS. These basic components of physical verification are being augmented by an expansive set of yield analysis and critical feature identification capabilities, as well as layout enhancements, and printability and performance validation, all of which Mentor addresses with the DFM tools of the Calibre nm Platform. Building on our powerful, production-proven Hyperscaling architecture, we deliver the broadest, most accurate, and best performing DFM solutions in the industry. Because the Calibre platform is built on standard open database interfaces, it brings production-proven DFM capabilities to our customers independent of the design creation environment they use.


Critical Area Analysis 
Calibre YieldAnalyzer performs critical area analysis (CAA) on all base and interconnect layers of a design. CAA identifies those areas of an integrated circuit layout with higher than average vulnerability to random particle defects that can create a short or open in areas with close spacing of layout features. Calibre YieldAnalyzer also performs critical feature analysis (CFA), a flexible extension to traditional recommended rules analysis, by employing a model-based approach that automatically plugs layout measurements into yield-related equations to identify areas of a physical design that have higher sensitivity to variations across the manufacturing process window. By integrating random (CAA) and systematic (CFA) process analysis, the Calibre nm Platform accounts for the combined impact of these effects on design manufacturability and enables designers to prioritize and guide manufacturability improvement in light of a wide spectrum of yield limiters.

 

Litho-Friendly Design 
Calibre YieldAnalyzer’s model-based CAA/CFA methodology complements the Calibre LFD™ litho-friendly design solution. Calibre LFD™ provides the ability to run simulations to see how a layout will print under a particular lithographic process window. Calibre LFD allows designers to achieve an “LFD clean” as well as a “DRC clean” sign-off to ensure high yields for advanced process nodes. Calibre® YieldEnhancer offers an automated approach to layout enhancements that will improve yield. It implements enhancements by taking advantage of white space, improving yield without sacrificing area. To balance performance, YieldEnhancer offers both a net-aware capability and back annotation to the design database. To determine the impact on yield, YieldEnhancer works with Calibre YieldAnalyzer to measure the impact of the layout modification.


Calibre nm Platform 
Mentor is continuing to extend the Calibre nm Platform to address all the needs of physical verification, DFM and post-tapeout physical design improvement. We invest heavily to ensure that our platform and tools are tightly integrated with each other and all major design environments, so users can have the flexibility to create optimum DFM flows while protecting their existing EDA investment.


Calibre DFM Features

Hierarchical Processing Engine
The underlying hierarchical processing engine ensures robust testing and implementation across all applications, while providing best-in-class runtimes.


Rapid Development 
Common design platform integration enables rapid deployment of all Calibre nm Platform applications into the user’s design environment.


Custom Design and Verification Environments
Integrated scripting environment across all applications (SVRF and TVF) allow users to customize their design and verification environment to suit the specific and evolving needs of their design teams.

 
Hyperscaling Technology
Hyperscaling technology brings superior scalability and lightening fast run times for computationally intense applications, while reducing capital expenditures by extending the useful life of existing shared memory processor systems, and fully utilizing inexpensive distributed rack systems.

 

Calibre DFM Products

Calibre LFD™
Calibre LFD is the first production-proven EDA tool to address the urgent issue of how to manage lithographic process variability in the early stages of design creation.

 

Calibre YieldAnalyzer
Calibre YieldAnalyzer integrates random (critical area) and systematic (critical feature) process variability analysis using model-based algorithms that automatically plug layout measurements into yield-related equations to help you identify areas of your physical design that have higher sensitivity to variations across the manufacturing process window.

 

Calibre YieldEnhancer
Calibre® YieldEnhancer offers an automated approach to layout enhancements that will improve yield.

 

Calibre CMPAnalyzer
Calibre CMPAnalyzer enhances systematic and parametric yield at smaller process nodes by simulating the changes in thickness and resistance variability, and by using automated fill capabilities to reduce resistance variability while minimizing capacitance.

Products A to Z - IC Design

ADiT 
Fast-SPICE simulator built specifically for analog and mixed-signal applications.

 

ADiT Rail

ADiT Rail, enhances ADiT with power integrity (IR) and electromigration analysis capabilities.

 

Analog FastSPICE  (AFS)

The world’s fastest nanometer circuit verification platform for analog, RF, mixed-signal, and custom digital circuits.

 

Calibre Automatic Waivers

Calibre® Automatic Waiver provides automated recognition and removal of waived design rule violations during DRC. Calibre Automatic Waivers eliminates costly time and effort from the verification process, and ensures accurate processing of all waiver information on every DRC run.


Calibre nmLVS
The industry-standard physical verification tool for layout vs. schematic comparison combines accurate circuit verification with fast runtimes and interactive debugging.


Calibre CMPAnalyzer
Calibre CMPAnalyzer enhances systematic and parametric yield at smaller process nodes by simulating the changes in thickness and resistance variability, and by using automated fill capabilities to reduce resistance variability while minimizing capacitance


Calibre DESIGNrev™

The Calibre DESIGNrev layout editor speeds full-chip design completions and tape-outs by rapidly loading, displaying and saving large GDSII and OASIS files.


Calibre Interactive™
The Calibre Interactive™ invocation GUI provides users with fast and easy access to the Calibre® tool suite, enabling designers to perform physical verification and parasitic extraction from within their familiar IC design environment.


Calibre LFD™
Calibre LFD is the first production-proven EDA tool to address the urgent issue of how to manage lithographic process variability in the early stages of design creation.


Calibre nmDRC 
The industry standard for design rule checking provides fast cycle times and innovative design rule capabilities.


Calibre PERC
Industry’s only programmable electrical rule checking (PERC) tool designed to address advanced verification requirements to ensure optimal design yield and improve reliability.

 

Calibre RealTime

Calibre® RealTime enables on-demand Calibre signoff design rule checking (DRC) for custom and analog/mixed-signal design flows, improving both design speed and the quality of results by providing immediate feedback on design rule violations and recommended rule compliance.


Calibre RVE™
Calibre RVE™ provides a graphical results viewing environment that can be used with all Calibre tools and popular design layout tools to reduce debug time by visually identifying design errors instantly in the user’s own design environment.

 

Calibre xACT 3D

Calibre® xACT 3D delivers high performance parasitic RC extraction featuring the reference-level accuracy of a deterministic field solver combined with the production turnaround performance of traditional rule-based extraction tools.


Calibre xL
Full-chip, fast, and accurate extraction of frequency dependent loop inductance and loop resistance and automatically accounts for return path change with frequency. Fully integrated with Calibre nmLVS and xRC.


Calibre xRC
Calibre xRC™ offers a robust parasitic extraction tool that delivers accurate parasitic data for comprehensive and accurate post-layout analysis and simulation.


Calibre YieldAnalyzer 
Calibre YieldAnalyzer integrates random (critical area) and systematic (critical feature) process variability analysis using model-based algorithms that automatically plug layout measurements into yield-related equations to help you identify areas of your physical design that have higher sensitivity to variations across the manufacturing process window.


Calibre YieldEnhancer
Calibre® YieldEnhancer offers an automated approach to layout enhancements that will improve yield.


Eldo Classic
Eldo Offers numerous simulation and modeling options that deliver high-performance and high-speed simulation with superior accuracy

 

Eldo Premier

Mentor’s new Faster-SPICE product, addresses the primary concerns of analog and mixed-signal designers, providing increased performance and capacity, especially for very large circuits, without sacrificing accuracy.


Eldo RF
Eldo RF : Transistor-level simulator for RF IC designs.


IC Station
IC Station SDL enables automated creation of layout data, while maintaining the relationship between layout and schematic, reducing design cycle time and assuring correct-by construction layout.


IC Station 
IC Station SDL enables automated creation of layout data, while maintaining the relationship between layout and schematic, reducing design cycle time and assuring correct-by construction layout.


ICassemble
ICassemble provides a robust set of features for floor planning, top-level assembly and interactive routing.


ICgraph 
ICgraph Supports an extensive set of editing functions for efficient, accurate polygon editing.


Olympus-SoC
Olympus-SoC is a complete IC design-for-variability implementation solution targeted at 65nm/45nm designs.

 

Pyxis Implement

Pyxis Implement, part of Mentor's new Pyxis Custom IC Design Platform, provides a highly productive environment for correct by construction layout entry and editing.

 

Pyxis Layout

Pyxis Layout, part of Mentor's new Pyxis Custom IC Design Platform, provides a fast and flexible environment for layout entry and editing.

 

Pyxis Schematic

Pyxis Schematic, part of Mentor's new Pyxis Custom IC Design Platform, provides a powerful and easy-to-use design entry environment with advanced capabilities that boost designer productivity.


Questa ADMS 
Language-neutral, mixed-signal simulator that enables top-down design and bottom-up verification of multi-million gate analog/mixed-signal System-on-Chip designs. 

 

Questa ADMS RF

Integrated RF and Mixed Signal Simulation for Complete Verification of RF-DSP Systems.





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