TANNER AMS IC DESIGN

Tanner Analog/Mixed-Signal IC Design Flow

Affordable, integrated analog/mixed-signal design flow that is easy to customize to your environment

Tanner AMS IC design flow (formerly HiPer Silicon AMS IC design flow) supports analog/mixed-signal design in one highly-integrated, end-to-end flow. Engineers can perform top-down, mixed-signal simulation or co-simulation, synthesis with DFT support, place and route, and high-speed, “sign-off ready” timing analysis for tape-out, within one cost-effective, unified flow.

 

  • OpenAccess, LEF/DEF, Liberty and SDF support
  • Simulate combined netlists: behavioral models, block-level RT/gate and transistor-level blocks
  • Debugging and support of advanced verification with SystemC and System Verilog
  • Proven, compatible synthesis with DFT support
  • Hierarchical DRC and netlist extraction with Calibre® compatibility
  • All-angle design rule checking (DRC) with interactive and real-time DRC
  • Foundry PDK support

 

 

Design and Simulation

Tanner S-Edit Schematic Capture

User-friendly schematic capture environment for even the most complex analog/mixed-signal designs. Learn More ►

 

Tanner T-Spice Simulation

Fast, accurate, foundry-proven simulation for demanding analog/mixed-signal designs. Learn More ►

 

Tanner Waveform Viewer

Intuitive interface for viewing, comparing and analyzing simulation results. Learn More ►

 

Layout

Tanner L-Edit IC Layout

A complete analog/mixed-signal IC physical design environment that is flexible and highly configurable. Learn More ►

 

Tanner Place and Route

Integrated digital place-and-route tool that speeds development of AMS designs. Learn More ►

 

Verification

Tanner Verify DRC and LVS

Comprehensive AMS IC design-rule checking (DRC) and netlist extraction that's fast and easy to use. Learn More ►

 

Tanner Parasitic Extraction

Fast, accurate extraction of circuit parasitics to model device behavior and verify design performance. Learn More ►

 

  Tanner AMS IC Design Flow Datasheet ►

 

  Tanner T-Spice AMS Simulation Datasheet ►

TANNER ANALOG IC DESIGN

Tanner Analog IC Design Flow

Complete, integrated analog design flow that is flexible and easy to use, speeding your time to working silicon

The Tanner Analog IC design environment (formerly HiPer Silicon Analog design flow) increases productivity from design, simulation, implementation, physical layout and verification, to foundry-proven tape-out.

 

  • OpenAccess and iPDK support
  • Accurate SPICE simulator compatible with HSPICE and Verilog-A
  • View simulation results directly on the schematic
  • Complete hierarchical layout editor with SDL and manual-assisted routing
  • Real-time, interactive DRC
  • Automatically generates current mirrors, differential pairs, and arrays
  • Calibre®-compatible, hierarchical DRC and netlist extraction 
  • Extract RC parasitics with fast 2D or ultra-accurate 3D

 

Design and Simulation

Tanner S-Edit Schematic Capture

User friendly schematic capture environment for even the most complex analog/mixed-signal designs. Learn More ►

 

Tanner T-Spice Simulation

Fast, accurate, foundry-proven simulation for demanding analog/mixed-signal designs. Learn More ►

 

Tanner Waveform Viewer

Intuitive interface for viewing, comparing and analyzing simulation results. Learn More ►

 

Layout

Tanner L-Edit IC Layout

A complete analog/mixed-signal IC physical design environment that is flexible and highly configurable. Learn More ►

 

Verification

Tanner Verify DRC and LVS

Comprehensive AMS IC design-rule checking (DRC) and netlist extraction that's fast and easy to use. Learn More ►

 

Tanner Parasitic Extraction

Fast, accurate extraction of circuit parasitics to model device behavior and verify design performance. Learn More ►

 

 T-Spice Simulation Datasheet ►

TANNER MEMS DESIGN FLOW

Tanner MEMS Design Flow

Affordable, easy-to-use 3D MEMS design environment for faster time to market

Tanner MEMS design flow delivers 3D MEMS design and fabrication support in one unified environment, and makes it easy to integrate MEMS devices with analog/mixed-signal processing circuitry on the same IC. Foundry-proven, it enhances the manufacturability of MEMS devices via mechanical, thermal, acoustic, electrical, electrostatic, magnetic and fluid analyses.

 

  • Create a MEMS 3D model from layout
  • Highly programmable layout editor with MEMS-friendly capabilities, such as curved polygons
  • Design rule checking for MEMS manufacturability
  • System-level simulation of IC design and MEMS devices
  • Complete layer & design geometry visualization
  • Automatically generate behavioral models of your MEMS devices
  • Import DXF with boundary reconstruction, export DXF
  • Available for Windows or Linux

 

Addressing the challenges of IoT Design

Internet of Things (IoT) designs mesh together several design domains in order to successfully develop a product that interfaces real-world activity to the internet. Individually, these design domains are challenging for today’s engineers. Bringing them all together to create an IoT product can place extreme pressure on design teams. Via this whitepaper the challenges of IoT Design are addressed. The fundamental challenge of IoT design is working in four design domains; analog, digital, RF, and MEMS. The Tanner design flow is architected to seamlessly work in any of the design domains by employing an integrated design flow for design, simulation, layout, and verification.

 

Addressing the Challenges of IoT Design

 

Features

 

Advanced 3D analysis tools

Supports mechanical, thermal, acoustic, electrical, electrostatic, magnetic and fluid analyses.

 

Complex polygon Boolean operations

Reduces errors and increases productivity.

 

Automatic layout generation with parameterized cells

Cells can be compiled for speed and/or distribution, programmed in C++ or Tcl. Supports external interfaces.

 

Advanced mask layout and verification flow

Support for a wide variety of MEMS foundry-proven process support available.

TANNER S-EDIT SCHEMATIC CAPTURE

Tanner S-Edit Schematic Capture

User-friendly schematic capture environment for even the most complex analog/mixed-signal designs

Tanner S-Edit schematic capture increases your design productivity while handling the most complex IC designs. This powerful environment supports fast, 64-bit rendering and cross-probing between schematic, layout, and LVS reporting at net and device levels. 

 

  • Industry-standard support including tight SPICE simulation integration and waveform cross-probing
  • Directly view operating point simulation results in the schematic
  • Cross-probe between schematic, layout and LVS report with net/device highlighting
  • Configurable schematic Electrical Rule Checks (ERC)
  • Advanced array and bus support
  • Integrated with Tanner L-Edit IC to speed the layout and ECO process
  • Available for Windows and Linux

 

Features

 

Easy to use

Intuitive, with an easy learning curve that gets you up and running quickly

 

Property callbacks and multiple views per cell

Including SPICE, schematic, Verilog, Verilog-A and Verilog-AMS views

 

Industry-standard import and export support

  • Export to SPICE, EDIF, Verilog, and VHDL
  • Import from OpenAccess, and EDIF, with automatic conversion of files from Mentor and other third-party tools

 

 Tanner S-Edit Schematic Capture Datasheet ►

TANNER T-SPICE

Tanner T-Spice Simulation

Fast, accurate, foundry-proven simulation for demanding analog/mixed-signal designs

Tanner T-Spice simulation integrates easily with other design tools and is compatible with industry-leading standards. It improves simulation accuracy with advanced modeling, multi-threading support, device-state plotting, real-time waveform viewing, and analysis, and a command wizard for simple SPICE syntax creation.

 

  • Fast, accurate analog/mixed-signal circuit simulation with support for multi-threading
  • Accurately characterize circuit behavior with virtual data measurements, parameter sweeping, Monte Carlo, DC/AC, and transient-noise analysis
  • Supports Levenberg-Marquardt non-linear optimizer, plot statements and parameter definitions, plus bit or bus logic waveform inputs
  • Lowest total cost of ownership in the industry
  • Available for Windows or Linux

 

Features

 

Intuitive and easy to use

Fast learning curve gets your designers up to speed quickly

 

Foundry-proven

  • RTL to GDSII, PDKs, and foundry process support
  • Supports PSP, BSIM3.3 & 4.6, BSIM SOI 4.0, EKV 2.6, MOS 9, RPI a-SI and Poly-Si TFT, VBIC, and MEXTRAM models

 

Supports key industry standards

  • HSPICE- and PSpice-compatible syntax
  • Verilog-A and Verilog-AMS support for advanced modeling- create customized models of any device

 

 T-Spice Simulation Datasheet ►

TANNER WAVEFORM VIEWER

Tanner Waveform Viewer

Intuitive interface for viewing, comparing and analyzing simulation results

Tanner Waveform Viewer (formerly known as W:Edit) provides an intuitive multiple-window, multiple-chart interface for easy viewing of waveforms and data in highly configurable formats.

 

  • Dynamically linked to Tanner T-Spice simulation and Tanner S-Edit schematic capture 
  • Waveform cross-probing directly in the schematic editor
  • Easily handles large (10GB+) data files
  • Available for Windows or Linux
  • Create new traces based on mathematical expressions of other traces for advanced analysis and easy comparison with measured data max, min, average, intersect, rms, over/undershoot, amplitude, error, crossing, delay, period, frequency, rise/falltime, jitter, pulse width, settling time, integral, derivative, duty cycle, and slew rate

 

Features

 

Automatically calculate & display FFT results

  • dB or linear magnitude
  • Wrapped or unwrapped phase
  • Use for real or imaginary parts


Intuitive, easy-to-use features

  • Dynamic annotations
  • Scripting
  • High-performance trace navigator


Run-time updates

See simulation results as they are being generated

 

TANNER L-EDIT IC

Tanner L-Edit IC Layout

A complete analog/mixed-signal IC physical design environment that is flexible and highly configurable

Create layouts that match the schematic the first time, maximizing efficiency and reducing the CAD manager’s support burden. Get up and running easily with platform independence and flexible licensing. Reduce manual routing with:

 

  • Real-time net flylines
  • Nets & pins tracking
  • Geometry marking/highlighting/by net
  • ECO tracking
  • Available for Windows and Linux

 

Features

 

Complete hierarchical physical layout 

Rich environment with a host of ease-of use features, including:

  • Object-snapping
  • Node highlighting
  • Macro support
  • Layout generators

 

Supports critical industry standards

  • OpenAccess read/write
  • Schematic-driven layout (SDL) support
  • Uses netlist files in T-Spice HSPICE, PSpice, structural Verilog, or CDL formats

 

Optimized performance

Fast rendering speeds and interactive, real-time design rule checking (DRC)

 

Extensive array of tool options and add-ons

Extend Tanner L-Edit IC capabilities with specialty tools and modules, including Tanner SDL Router.

 

Direct Calibre®/Calibre RVE support with EVI

Tanner External Verification Interface (EVI) seamlessly integrates with the Calibre tool suite, allowing you to leverage investments in both environments

 

 Tanner L-Edit Datasheet ►

 

 Tanner SDL Router ►

TANNER PLACE & ROUTE

Tanner Place & Route

Integrated, flexible digital place & route tool that speeds development of analog/mixed-signal designs

Tanner Place & Route is optimized for the needs of 'big' analog / 'little' digital mixed-signal designs on typical analog process nodes. It is a critical part of the Tanner AMS end-to-end flow for analog/mixed-signal designs. Highly flexible, Tanner Place & Route delivers unparalleled flexibility during every phase of the flow.

 

  • Clock-tree synthesis
  • SDF timing extraction
  • Interactive, cost-effective tool
  • Available for Windows and Linux

 

Features

 

Supports standard digital formats

  • Clock-tree synthesis
  • SDF timing extraction
  • Interactive, cost-effective tool
  • Available for Windows and Linux

 

Designed for analog specialty process nodes

Tanner Place and Route tool was developed for analog specialty process technologies on nodes of 90nm and above, with 10k to 50k gates of digital logic.

 

Intuitive, easy to use

Fast, easy learning curve allows you to get up to speed quickly on the tool and maximize productivity.

 

 Place and Route Datasheet ►

TANNER VERIFY

Tanner Verify DRC and LVS

Comprehensive analog/mixed-signal IC design-rule checking (DRC) and netlist extraction that’s fast and easy to use

Tanner Verify DRC and LVS is a comprehensive solution for analog/mixed-signal IC Design Rule Checking (DRC) and netlist extraction. Its 64-bit engine enables fast, simple debugging through DRC and netlist extraction, and uses advanced hierarchical algorithmic techniques to provide optimal performance for your designs.

 

  • Execute multiple DRC command files sequentially in a single DRC run
  • Run batch DRC or netlist extraction on multiple cells
  • Performs Electrical Rule Checks (ERC), such as antenna checks
  • Extract a SPICE netlist from layout for LVS command file
  • Perform LVS with cross-probing from SPICE and LVS results to layout or schematic with enhanced SPICE file navigation
  • Integration with Tanner L-Edit IC layout for precision DRC
  • Available on Windows or Linux

 

Features

 

Intuitive, easy-to-use interface

Unified environment and fast learning curve helps you quickly become productive.

 

Enhanced violation viewing and editing

View top cell or violation cell and, rule/violation distance, then mark violations as they are fixed. Fix violations while DRC is running.

 

Native support for popular foundry file types

Run Calibre® and other industry-standard foundry files without conversion or modification.

 

 Tanner Verify Datasheet ►

TANNER PARASITIC EXTRACTION

Tanner Parasitic Extraction

Fast, accurate extraction of circuit parasitics to model device behavior and verify design performance

Tanner Parasitic Extraction (formerly HiPer PX Parasitic Extraction) extracts circuit parasitics so you can get the design right the first time with accurate interconnect modeling. It includes fast 2D extraction, accurate 3D modeling and the ability to quickly extract simulation-ready SPICE netlists from layout, including devices and interconnect parasitics.

 

  • Quickly extract simulation-ready SPICE netlists from layout, including devices (MOSFETs, bipolars, etc.) and interconnect parasitics
  • Perform hierarchical, flat or mixed extraction
  • Integrated with Tanner L-Edit IC , it can be run from Tanner L-Edit IC interactive GUI
  • Available for Windows and Linux platforms

 

Features

 

Extract accurate, complete parasitic networks

Extracts networks for node, vertical/lateral coupling capacitance and interconnect resistance.

 

Intuitive, fast learning curve

Easy to use, ensuring you can become productive quickly.

 

Improved accuracy saves simulation time

Improved interconnect modeling accuracy to help you reduce silicon area, power consumption, and parasitic netlists.

 

 Tanner Parasitic Extraction Datasheet ►





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