MX001

VHDL programming language

Course Overview

Duration: 3 days    

This course will introduce VHDL programming language and its use in logic design; it will allow you to understand VHDL Basics, different data types, Statements and functions.

You will learn

  • VHDL overview
  • Timing Optimization
  • Area Optimization
  • High Level Design
  • Clock Domains
  • Synthesis Optimization
  • Static Timing Analysis

 

MX002

FPGA Design

Courses Overview

Duration: 5 days

This training will help you acquire the skills needed to maximize your usage of FPGA Advantage and improve your FPGA design process. This course will teach you how to create custom designs from concept to silicon. The lecture modules will demonstrate the FPGA Advantage design flow from the basics of creating a graphical design in HDL Designer Series, through verifying your design in the Questa® HDL simulator, to synthesizing and optimizing your design into a physical device with Precision RTL.

You will learn how to

  • Build conceptual HDL designs quickly using HDL Designer Series
  • Build HDL state machines, block diagrams, truth tables, and flow charts
  • Debug and verify your conceptual design using Questa®
  • Create test bench designs quickly
  • Synthesize your HDL design into a wide range of physical FPGAs using Precision RTL
  • Optimize your design for speed and area
  • Perform static timing analysis
  • Perform gate level verification, compare waveforms against RTL simulation
  • Introduction to Verification Plan
  • Code Coverage &Functional Coverage
  • Verification Management ( Regression Test Tracking)
  • Power Aware Verification

Prerequisites:

  • Basic knowledge of digital circuit design
  • VHDL Programming Language course MX001

 

MX003

IC Design to Tape Out (old IC flow)

Course Overview

Duration: 5 days

This course will provide all the knowledge needed to apply the power of ICstudio, Mentor’s integrated IC design environment, to your most challenging VLSI designs. As you progress through the course you will acquire the skills needed to manage your IC design project, capture and simulate your design, create the layout for your chip, use advanced interactive and automatic routing and floor planning tools, perform DRC and LVS verification, and use extracted parasitic data in post-layout simulation

You will learn how to

  • Create and modify ICstudio projects
  • Create and edit hierarchical schematics
  • Set up and run analog simulations
  • Create and edit hierarchical IC layouts
  • Use Schematic-Driven Layout (SDL) tools to automatically construct layouts
  • Add layout routing using interactive and automatic routing tools
  • Plan top-level block size and placement using comprehensive floorplanning tools
  • Verify layouts using Calibre DRC/LVS

 

Prerequisites:

 B.Sc. (Eng.) Electronics and Telecommunications Engineering.

 

MX004

Eldo Simulation

Course Overview

Duration: 3 days

Education Services can help you acquire the skills needed to maximize your usage of Eldo®/EldoRF and realize its full impact on your analog/mixed signal verification process. You will become familiar with tuning your circuit to use the best-suited algorithms and accuracy control options, perform measurements on various types of waveforms, choose the most appropriate statistical analyses, perform noise analyses, understand the concepts of optimization, and simulate your design taking aging effects. The lecture modules will guide you through the various advanced concepts and tools associated with Eldo.  

You will learn how to 

  • Setup, run simulation and interpret results in the EZwave Waveform Viewer
  • Control your simulation in many flexible ways
  • Extract information from the simulation
  • Choose the suitable noise analysis you need for your design
  • Perform standard analyses and parametric analysis
  • Use the most appropriate statistical analysis

 

MX005

EldoRF Simulation

Course Overview  

Duration: 3 days

Education Services can help you acquire the skills needed to maximize your usage of EldoRF and realize its full impact on your analog/mixed signal verification process. You will become familiar Mentor Graphics Eldo RF that provides the necessary performance and capacity breakthroughs for RF IC simulation. You will become familiar with the advanced analysis simulation algorithms to handle the multi GHZ signals in modern applications

You will learn how to 

  • Eldo Basics introduction
  • Eldo RF introduction and core Technology
  • Steady State Analysis
  • Steady State Noise Analysis
  • Large-Signal S-parameter Analysis
  • Steady-State Oscillator Analysis
  • SST Analysis Application for Frequency Dividers
  • Modulation Steady-State
  • Steady State AC and TF Analyses

 

Prerequisites:

  • B.Sc. (Eng.) Electronics and Telecommunications Engineering
  • Basic knowledge of RF.
  • Basic knowledge of analog circuit design.

 

MX006

Analog and Mixed Signal Modeling (VHDL-AMS Programming Language)

Course Overview 

Duration: 6 days 

In class the designer will learn the basics of the VHDL-AMS (IEEE 1076.1) hardware descriptor language and its efficient use for model creation, validation, and design reuse. The class is intended for analog, mixed-signal, and mixed-nature designers who want to discover what advantages high-level modeling brings to the design process. The three days of the class are spent on the basics of the VHDL-AMS language and teaching efficient modeling practices. 

You will learn how to 

  • Code models using the VHDL-AMS notation
  • Develop efficient mathematical models for encoding with VHDL-AMS
  • Digital Modeling and simulation (behavioral and Structural Language constructs)
  • Analog Modeling and Simulation in Time and Frequency Domain
  • Mixed Signal Modeling and Simulation
  • Write portable, reusable VHDL-AMS code.
  • Verify and test continuous, discrete event, and mixed signal models

 

Prerequisites:

  • B.Sc. (Eng.) Electronics and Telecommunications Engineering
  • Basic knowledge of analog circuit design.
  • Basic knowledge of digital circuit design.
  • Good knowledge of VHDL.

 

MX007

ICStation, Layout VLSI Designs

Course Overview 

Duration: 3 days 

Education Services can help you acquire the skills needed to maximize your usage of IC Station and realize its full impact on your layout process. This course will empower you to layout VLSI designs directly from the logic, check them for errors, and keep them current with the latest design changes. The lecture modules will guide you through the various concepts and tools associated with IC Station from the basics of creating polygons to more advanced topics like SDL.

You will learn how to 

  • Use ICgraph in both GE (Geometry Editing) and CBC (Correct by Construction) modes
  • Harness the power of Schematic Driven Layout (SDL)
  • Speed up your process using ICdevice.
  • Customize automatically generated devices for your specific layout needs
  • Use ICassemble to support every level of SoC design hierarchy - analog and digital
  • Use IC Station routing tools: Iroute, and ARoute to route leaf cells, sub-blocks, and block cells
  • Use the power of hierarchical design to automatically keep all designs up-to-date
  • Customize the user interface so the commands you use most are quickly accessible

 Prerequisites:

  • B.Sc. (Eng.) Electronics and Telecommunications Engineering.

 

MX008

Calibre nmDRC, Calibre nmLVS

Course Overview 

Duration: 2 days 

Calibre is the industry standard for Deep Submicron Physical Verification. Realize its full impact on your design process by attending the Education Services "Calibre nmDRC/nmLVS" course.

It will teach you to effectively use Mentor Graphics Calibre software in your layout verification flow and will empower you to analyze the Calibre nmDRC and Calibre nmLVS results successfully in coordination with a layout editor. 

The lecture modules will guide you through the various concepts underlying state-of-the-art layout verification techniques and specific aspects of the Calibre toolset. 

You will learn how to 

  • Use Calibre nmDRC and Calibre nmLVS proficiently in the flat and hierarchical modes
  • Debug the flat and hierarchical DRC and LVS results using Calibre RVETM (Results Viewing Environment) and a layout editor
  • Interpret the various specification statements in your rule file dealing with layout and source input, nmDRC and nmLVS results databases and reports, and other useful rule file statements
  • Interpret simple DRC checks such as width, spacing, and enclosure checks
  • Interpret complex, state-of-the-art DRC checks such as antenna checks and ERC checks
  • Perform netlist vs. netlist and layout vs. layout (LVL) comparisons
  • Identify and locate the following DRC-related problems: external spacing of edges on different or same layers; internal spacing of edges on different or same layers; measurement of geometry on one layer enclosed by geometry on another
  • Identify and locate the following LVS-related problems: shorts and opens, including those on power and/or ground nets; floating or isolated nets; pin swapping; device problems; soft-connections; and texting (naming) problems
  • Use the powerful Calibre Interactive Graphical User Interface
  • Apply incremental DRC capabilities to reduce overall verification time
  • Interface Calibre to tools from other vendors

Prerequisites:

  • B.Sc. (Eng.) Electronics and Telecommunications Engineering

 

MX009

Calibre XRC-Parasitic Extraction

Course Overview 

Duration: 1 day

Post-layout simulation is both necessary and expensive. As process nodes shrink, the job of extracting the parasitic required for post-layout simulation is becoming both more critical and more difficult. In-house expertise and foundry-supplied PDKs are no longer the solution; they are the starting point. Performing extraction using Calibre xRC requires that you fully understand the many trade-offs you must make as well as the analysis needs presented by your designs.

You will learn to 

  • Generate extracted netlists in three standard formats.
  • Take advantage of the Calibre xRC 3-stage extraction process to generate multiple parasitic networks from a single extraction run.
  • Review and interpret extraction results.

Prerequisites:

  • B.Sc. (Eng.) Electronics and Telecommunications Engineering

 

MX010

DXDesigner for Expedition PCB

Course Overview 

Duration: 2 days 

The DxDesigner for the Expedition PCB Flow course will help you to improve your knowledge and skills with Design Definition solutions. Using the DxDesigner tools suite, you will gain proficiency in project management with Dashboard, schematic capture with DxDesigner. You will also learn how to prepare your final schematic for interfacing with the Mentor Graphics Expedition PCB layout tool. 

 You will learn how to 

  • Use DxDesigner proficiently in the creation of flat and hierarchical schematic designs 
  •  Place wires and buses in the design to create net connections 
  •  Create symbols for your schematics through a variety of methods, including the Symbol Wizard 
  •  Effectively build intelligence into your design using properties 
  •  Compile, package and export your schematic to Expedition PCB for place and route 
  •  Use CES to create and assign constraints to your design and pass that information to Expedition 

Prerequisites:

  •  B.Sc. (Eng.) Electronics and Telecommunications Engineering
  •  Basic knowledge of electronics

 

MX011

Expedition PCB

Course Overview

Duration: 4 days

Expedition PCB Introduction presents the workflow and methods of laying out a printed circuit board using the latest version of Mentor Graphics Expedition PCB. From fundamental library concepts, to the PCB editor environment and the PCB layout process, you will gain hands-on experience in integrating a source schematic, placing and routing the board and outputting the fabrication data.

 You will learn how to

  • Create Padstacks, Cell (footprint) and Part (PDB) definitions, and build intelligence into components.    
  • Create a Layout Template.
  • Start a PCB Layout by integrating with a schematic design.
  • Define Board Geometry
  • Place parts, swap pins & gates and back annotate.
  • Verify the Layout with on-line and batch Design Rule Checking
  • Utilize the Constraint Editor System (CES) to define layout and routing constraints
  • Route, using both manual/interactive and automatic tools.
  • Add test points, Generate Plane data
  • Finalize the Silkscreen
  • Generate Gerber Data,Generate Drill Data  

Prerequisites:

  •  B.Sc. (Eng.) Electronics and Telecommunications Engineering
  •  Basic knowledge of electronics

 

MX012

HyperLynx Signal Integrity Analysis

Course Overview

Duration: 3 days

The HyperLynx Signal Integrity Analysis course was developed to help you understand basic signal integrity, crosstalk, EMI concepts and gain proficiency in signal integrity, crosstalk, and EMI analyses, pre and post layout.

 You will learn how to  

  • Create and simulate LineSim cell-based and free-form schematics
  • Investigate termination strategies
  • Investigate stack-up strategies
  • Translate design databases
  • Identify and debug SI and Crosstalk issues
  • Read eye diagrams and how to specify a mask
  • Simulate EMC and evaluate the results
  • Assign models and component values
  • Evaluate SI and Crosstalk issues
  • Translate PCB layout databases
  • Run BoardSim simulations interactively and in batch mode
  • Run BoardSim for both single and multi-board projects
  • Evaluate batch mode simulation reports to identify potential problems

Prerequisites:

  • B.Sc. (Eng.) Electronics and Telecommunications

 

MX013

I/O Designer (FPGA-PCB Integration)

Courses Overview

Duration: 1 day

As the FPGA devices grew larger, it is harder to maintain consistency between the FPGA and PCB design flows. I/O Designer bridges the gap between the two design flows. This course offered by Mentor Graphics teaches you how to manage the data and monitor the changes between the two design flows while maintaining consistency. Both the lectures and hands-on labs provide you with skills necessary to use the tool efficiently in the design process, under the guidance of our industry expert instructors.

You will learn how to

  • Use I/O Designer in different design scenarios
  • Create an I/O Designer database
  • Assign signals read in from a HDL file to the FPGA device pins
  • Automatically unravel signals and buses based on the PCB floorplan
  • Create symbols using different fracturing schemes
  • Export the created symbols to a schematic tool
  • Update and synchronize the changes between the two design flows
  • Use I/O Designer to optimize Multi-FPGA Designs
  • Manage the database in a team design using version control mechanisms

Prerequisites:

  • Basic knowledge of digital circuit design and Electronics
  • FPGA Advantage MX002
  • Expedition PCB MX011

 

MX014

PADS PCB Design

Courses Overview 

Duration: 4 Days

- DXDesigner for PADS

The DxDesigner for the PADS Flow course will help you to improve your knowledge and skills with Design Definition solutions. Using the DxDesigner tools, you will gain proficiency in project management with Dashboard, schematic capture with DxDesigner. You will also learn how to prepare your final schematic for interfacing with the Mentor Graphics PADS layout tool. 

You will learn how to 

  • Use DxDesigner proficiently in the creation of flat and hierarchical schematic designs
  • Place wires and buses in the design to create net connections
  • Create symbols for your schematics through a variety of methods, including the Symbol Wizard
  • Effectively build intelligence into your design using properties
  • package and export your schematic to PADS for place and route

- PADS Layout/Router

The PADS Layout /Router course focuses on the workflow of printed circuit board layout, using Mentor Graphics PADS Layout application and completing connections using the PADS Router. You will be guided through the steps necessary to design a printed circuit board. Course highlights include creating physical components, adding or updating components, routing connections, generating reports and routing a sample printed circuit board using manual autoroute and interactive autoroute modes.

You will learn how to

  • Customize and work with the PADS Layout interface.
  • Create board outlines, cut outs and keepouts
  • Place parts manually
  • Customize and work with the PADS Router interface
  • Set Options and how to Prepare Batch Autorouting using the Routing Strategy
  • Assign Properties – Rules and Routing Preferences to the Design and its Objects  
  • Route, Fanout and Optimize (net connections) by Interactive Selection
  • Prepare Layer Direction, Corner and Quality Settings for Optimal Routing
  • Verify the designand generate Gerber Data

 

MX015

ASIC Standard Cell Design

Course Overview

Course Duration: 5 Days                                            

Standard cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. Cell-based ASICs (CBICs) make use of pre-designed, pre-tested, and pre-characterized logic cells such as AND gates, OR gates, multiplexers, and flip-flops for the design. These predefined cells are also referred to as standard cells

This course will provide the basic knowledge needed for designing Standard Cells ASICs with the ASIC Design Kit (ADK) and Mentor Graphics Tools.

You will learn

  • How to create VHDL Designs.
  • Simulating and Verifying functionality of RTL design
  • ow  to use Leonardo Spectrum for synthesizing and optimizing the area, speed of the design based on the target technology
  • How to create the layout for your standard cell ASIC design
  • Perform DRC and LVS verification, and use extracted parasitic data in post-layout simulation

Prerequisites:

  • B.Sc. (Eng.) Electronics and Telecommunications Engineering
  • Basic knowledge of digital circuit design.
  • Good knowledge of VHDL.

 

MX021

Pyxis Schematic, analog simulation & Layout Design

Course Overview

Duration: 5 days

This course will provide all the knowledge needed to apply the power of Pyxis, Mentor’s integrated IC design environment, to your most challenging IC designs. As you progress through the course you will acquire the skills needed to manage your IC design project, capture and simulate your design, create the layout for your chip, use advanced interactive and automatic routing and floor planning tools, perform DRC and LVS verification, and use extracted parasitic data in post-layout simulation

You will learn how to

  • Create and modify Pyxis projects
  • Create and edit hierarchical schematics
  • Set up and run analog simulations
  • Create and edit hierarchical IC layouts
  • Use Schematic-Driven Layout (SDL) tools to automatically construct layouts
  • Add layout routing using interactive and automatic routing tools
  • Plan top-level block size and placement using comprehensive floorplanning tools
  • Verify layouts using Calibre DRC/LVS
  • Extract parasitic data and use extracted parasitic data in simulations

 

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